Computer Aided Verification (Record no. 57477)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04407nam a22005895i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-319-21668-3 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200421112222.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 150713s2015 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319216683 |
| -- | 978-3-319-21668-3 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 005.1015113 |
| 245 10 - TITLE STATEMENT | |
| Title | Computer Aided Verification |
| Sub Title | 27th International Conference, CAV 2015, San Francisco, CA, USA, July 18-24, 2015, Proceedings, Part II / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XVIII, 469 p. 107 illus. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Lecture Notes in Computer Science, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | SMT Techniques and Applications -- POLING: SMT Aided Linearizability Proofs -- Finding Bounded Path in Graph Using SMT for Automatic Clock Routing -- Cutting the Mix -- The Inez Mathematical Programming Modulo Theories Framework -- Using Minimal Correction Sets to More Efficiently Compute Minimal Unsatisfiable Sets -- Deciding Local Theory Extensions via E-matching -- HW Verification -- Modular Deductive Verification of Multiprocessor Hardware Designs -- Word-Level Symbolic Trajectory Evaluation -- Verifying Linearizability of Intel� Software Guard Extensions -- Synthesis Synthesis Through Unification -- From Non-preemptive to Preemptive Scheduling Using Synchronization Synthesis -- Counterexample-Guided Quantifier Instantiation for Synthesis in SMT -- Deductive Program Repair -- Quantifying Conformance Using the Skorokhod Metric -- Pareto Curves of Multidimensional Mean-Payoff Games -- Termination -- Conflict-Driven Conditional Termination -- Predicate Abstraction and CEGAR for Disproving Termination of Higher-Order Functional Programs -- Complexity of Bradley-Manna-Sipma Lexicographic Ranking Functions -- Measuring with Timed Patterns -- Automatic Verification of Stability and Safety for Delay Differential Equations -- Time Robustness in MTL and Expressivity in Hybrid System Falsification -- Concurrency -- Adaptive Concretization for Parallel Program Synthesis -- Automatic Completion of Distributed Protocols with Symmetry -- An Axiomatic Specification for Sequential Memory Models -- Approximate Synchrony: An Abstraction for Distributed Almost-Synchronous Systems -- Automated and Modular Refinement Reasoning for Concurrent Programs. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | The two-volume set LNCS 9206 and LNCS 9207 constitutes the refereed proceedings of the 27th International Conference on Computer Aided Verification, CAV 2015, held in San Francisco, CA, USA, in July 2015. The total of 58 full and 11 short papers presented in the proceedings was carefully reviewed and selected from 252 submissions. The papers were organized in topical sections named: model checking and refinements; quantitative reasoning; software analysis; lightning talks; interpolation, IC3/PDR, and Invariants; SMT techniques and applications; HW verification; synthesis; termination; and concurrency. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Kroening, Daniel. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Păsăreanu, Corina S. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-3-319-21668-3 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2015. |
| 336 ## - | |
| -- | text |
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| -- | computer |
| -- | c |
| -- | rdamedia |
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| -- | online resource |
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| -- | text file |
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| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer organization. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Software engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer logic. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Mathematical logic. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer Science. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logics and Meanings of Programs. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Software Engineering/Programming and Operating Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Mathematical Logic and Formal Languages. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer Systems Organization and Communication Networks. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 0302-9743 ; |
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