Architecture-aware optimization strategies in real-time image processing / (Record no. 68875)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 05046cam a2200577Ii 4500 |
| 001 - CONTROL NUMBER | |
| control field | on1008962948 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220711203418.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 171102s2017 enk ob 001 0 eng d |
| 019 ## - | |
| -- | 1009067879 |
| -- | 1015357691 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781119467144 |
| -- | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 1119467144 |
| -- | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781119467243 |
| -- | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 1119467241 |
| -- | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | (print) |
| 037 ## - | |
| -- | 9781119467144 |
| -- | Wiley |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 006.4/2 |
| 100 1# - AUTHOR NAME | |
| Author | Li, Chao, |
| 245 10 - TITLE STATEMENT | |
| Title | Architecture-aware optimization strategies in real-time image processing / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 1 online resource. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | ""Cover""; ""Half-Title Page""; ""Title Page""; ""Copyright Page""; ""Contents""; ""Preface""; ""1. Introduction of Real-time Image Processing""; ""1.1. General image processing presentation""; ""1.2. Real-time image processing""; ""2. Hardware Architectures for Real-time Processing""; ""2.1. History of image processing hardware platforms""; ""2.2. General-purpose processors""; ""2.3. Digital signal processors""; ""2.4. Graphics processing units""; ""2.5. Field programmable gate arrays""; ""2.6. SW/HW codesign of real-time image processing"" |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | ""2.7. Image processing development environment description""""2.8. Comparison and discussion""; ""3. Rapid Prototyping of Parallel Reconfigurable Instruction Set Processor for Efficient Real-Time Image Processing""; ""3.1. Context and problematic""; ""3.2. Related works""; ""3.3. Design exploration framework""; ""3.4. Case study: RISP conception and synthesis for spatial transforms""; ""3.4.1. Digital DCT algorithm implementations""; ""3.4.2. Rapid prototyping of DCT RISP conception""; ""3.4.3. RISP simulation and synthesis for 2D-DCT"" |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | ""3.5. Hardware implementation of spatial transforms on an FPGA-based platform""""3.6. Discussion and conclusion""; ""4. Exploration of High-level Synthesis Technique""; ""4.1. Introduction of HLS technique""; ""4.2. Vivado_HLS process presentation""; ""4.2.1. Control and datapath extraction""; ""4.2.2. Scheduling and binding""; ""4.3. Case of HLS application: FPGA implementation of an improved skin lesion assessment method""; ""4.3.1. KMGA method description""; ""4.3.2. KMGA method optimization""; ""4.3.3. HCR-KMGA implementation onto FPGA using HLS technique"" |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | ""4.3.4. Implementation evaluation experiments""""4.4. Discussion""; ""5. CDMS4HLS: A Novel Source-To-Source Compilation Strategy for HLS-Based FPGA Design""; ""5.1. S2S compiler-based HLS design framework""; ""5.2. CDMS4HLS compilation process description""; ""5.2.1. Function inline""; ""5.2.2. Loop manipulation""; ""5.2.3. Symbolic expression manipulation""; ""5.2.4. Loop unwinding""; ""5.2.5. Memory manipulation""; ""5.3. CDMS4HLS compilation process evaluation""; ""5.3.1. Performances improvement evaluation""; ""5.3.2. Comparison experiment""; ""5.4. Discussion"" |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | ""6. Embedded Implementation of VHR Satellite Image Segmentation""""6.1. LSM description""; "" 6.1.1. Background""; ""6.1.2. Level set equation""; ""6.1.3. LBM solver""; ""6.2. Implementation and optimization presentation""; ""6.2.1. Design flow description""; ""6.2.2. Algorithm analysis""; ""6.2.3. Function inline""; ""6.2.4. Loop manipulation""; ""6.2.5. Symbol expression manipulation""; ""6.2.6. Loop unwinding""; ""6.3. Experiment evaluation""; ""6.3.1. Parameter configuration""; ""6.3.2. Function verification""; ""6.3.3. Optimization evaluation""; ""6.3.4. Performance comparison"" |
| 590 ## - LOCAL NOTE (RLIN) | |
| Local note | John Wiley and Sons |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Digital techniques. |
| 650 #7 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Digital techniques. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Balla-Arabe, Souleymane, |
| 700 1# - AUTHOR 2 | |
| Author 2 | Yang, Fan, |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1002/9781119467243 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | London, UK : |
| -- | ISTE, Ltd. ; |
| -- | Hoboken, NJ : |
| -- | Wiley, |
| -- | 2017. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 588 0# - | |
| -- | Online resource; title from PDF title page (John Wiley, viewed November 9, 2017). |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Image processing |
| 650 #7 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | COMPUTERS / General. |
| 650 #7 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Image processing |
| -- | (OCoLC)fst00967508 |
| 994 ## - | |
| -- | 92 |
| -- | DG1 |
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