Using Artificial Neural Networks for Analog Integrated Circuit Design Automation (Record no. 78733)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04105nam a22005775i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-030-35743-6 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220801220609.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 191211s2020 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783030357436 |
| -- | 978-3-030-35743-6 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Rosa, João P. S. |
| 245 10 - TITLE STATEMENT | |
| Title | Using Artificial Neural Networks for Analog Integrated Circuit Design Automation |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2020. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XVIII, 101 p. |
| 490 1# - SERIES STATEMENT | |
| Series statement | SpringerBriefs in Applied Sciences and Technology, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Introduction -- Related Work -- Overview of Artificial Neural Networks (ANNs) -- On the Exploration of Promising Analog IC Designs via ANNs -- ANNs as an Alternative for Automatic Analog IC Placement -- Conclusions. . |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book addresses the automatic sizing and layout of analog integrated circuits (ICs) using deep learning (DL) and artificial neural networks (ANN). It explores an innovative approach to automatic circuit sizing where ANNs learn patterns from previously optimized design solutions. In opposition to classical optimization-based sizing strategies, where computational intelligence techniques are used to iterate over the map from devices’ sizes to circuits’ performances provided by design equations or circuit simulations, ANNs are shown to be capable of solving analog IC sizing as a direct map from specifications to the devices’ sizes. Two separate ANN architectures are proposed: a Regression-only model and a Classification and Regression model. The goal of the Regression-only model is to learn design patterns from the studied circuits, using circuit’s performances as input features and devices’ sizes as target outputs. This model can size a circuit given its specifications for a single topology. The Classification and Regression model has the same capabilities of the previous model, but it can also select the most appropriate circuit topology and its respective sizing given the target specification. The proposed methodology was implemented and tested on two analog circuit topologies. . |
| 700 1# - AUTHOR 2 | |
| Author 2 | Guerra, Daniel J. D. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Horta, Nuno C. G. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Martins, Ricardo M. F. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Lourenço, Nuno C. C. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-030-35743-6 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2020. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Signal processing. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computational intelligence. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Signal, Speech and Image Processing . |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computational Intelligence. |
| 700 1# - AUTHOR 2 | |
| -- | (orcid)0000-0002-1687-1447 |
| -- | https://orcid.org/0000-0002-1687-1447 |
| 700 1# - AUTHOR 2 | |
| -- | (orcid)0000-0002-8251-1415 |
| -- | https://orcid.org/0000-0002-8251-1415 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 2191-5318 |
| 912 ## - | |
| -- | ZDB-2-ENG |
| 912 ## - | |
| -- | ZDB-2-SXE |
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