Toward 5G Software Defined Radio Receiver Front-Ends (Record no. 80584)

000 -LEADER
fixed length control field 03661nam a22005295i 4500
001 - CONTROL NUMBER
control field 978-3-319-32759-4
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20220801222253.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 160621s2016 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783319327594
-- 978-3-319-32759-4
082 04 - CLASSIFICATION NUMBER
Call Number 621.3815
100 1# - AUTHOR NAME
Author Spiridon, Silvian.
245 10 - TITLE STATEMENT
Title Toward 5G Software Defined Radio Receiver Front-Ends
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2016.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XVII, 96 p. 50 illus., 20 illus. in color.
490 1# - SERIES STATEMENT
Series statement SpringerBriefs in Electrical and Computer Engineering,
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Overview of Wireless Communication in the Internet Age -- Defining the optimal architecture -- From High Level Standard Requirements to Circuit Level Electrical Specifications: A Standard Independent Approach -- Optimal Filter Partitioning -- Smart Gain Partitioning for Noise – Linearity Trade-Off Optimization -- SDRX Electrical Specifications -- A System Level Perspective of Modern Receiver Building Blocks -- Conclusions and Future Developers.
520 ## - SUMMARY, ETC.
Summary, etc This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion architecture. This allows readers give a power consumption budget to determine how much filtering is required on the receive path, by considering the ADC performance characteristics and the corresponding blocker diagram.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-319-32759-4
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
264 #1 -
-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2016.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuits.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Signal processing.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronics.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Signal, Speech and Image Processing .
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronics and Microelectronics, Instrumentation.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
-- 2191-8120
912 ## -
-- ZDB-2-ENG
912 ## -
-- ZDB-2-SXE

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