Neuro-inspired Computing Using Resistive Synaptic Devices (Record no. 80975)

000 -LEADER
fixed length control field 04350nam a22005055i 4500
001 - CONTROL NUMBER
control field 978-3-319-54313-0
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20220801222624.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 170421s2017 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783319543130
-- 978-3-319-54313-0
082 04 - CLASSIFICATION NUMBER
Call Number 621.3815
245 10 - TITLE STATEMENT
Title Neuro-inspired Computing Using Resistive Synaptic Devices
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2017.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XI, 269 p. 190 illus., 79 illus. in color.
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Chapter1: Introduction to Neuro-Inspired Computing using Resistive Synaptic Devices -- Part I: Device-level Demonstrations of Resistive Synaptic Devices -- Chapter2: Phase Change Memory based Synaptic Devices -- Chapter3: Pr0.7Ca0.3MnO3 (PCMO) based Synaptic Devices -- Chapter4: TaOx/TiO2 based Synaptic Devices -- Part II: Array-level Demonstrations of Resistive Synaptic Devices and Neural Networks -- Chapter5: Training and Inference in Hopfield Network using 10×10 Phase Change Synaptic Array -- Chapter6: Experimental Demonstration of Firing-Rate Neural Networks based on Metal-Oxide Memristive Crossbars -- Chapter7: Weight Tuning of Resistive Synaptic Devices and Convolution Kernel Operation on 12×12 Cross-Point Array -- Chapter8: Spiking Neural Network with 256×256 PCM Array -- Part III: Circuit, Architecture and Algorithm-level Design of Resistive Synaptic Devices based Neuromorphic System -- Chapter9: Peripheral Circuit Design Considerations of Neuro-inspired Architectures -- Chapter10: Processing-in-Memory Architecture Design for Accelerating Neuro-Inspired Algorithms -- Chapter11: Multi-layer Perceptron Algorithm: Impact of Non-Ideal Conductance and Area-Efficient Peripheral Circuits -- Chapter12: Impact of Non-Ideal Resistive Synaptic Device Behaviors on Implementation of Sparse Coding Algorithm -- Chapter13: Binary OxRAM/CBRAM Memories for Efficient Implementations of Embedded Neuromorphic Circuits.
520 ## - SUMMARY, ETC.
Summary, etc This book summarizes the recent breakthroughs in hardware implementation of neuro-inspired computing using resistive synaptic devices. The authors describe how two-terminal solid-state resistive memories can emulate synaptic weights in a neural network. Readers will benefit from state-of-the-art summaries of resistive synaptic devices, from the individual cell characteristics to the large-scale array integration. This book also discusses peripheral neuron circuits design challenges and design strategies. Finally, the authors describe the impact of device non-ideal properties (e.g. noise, variation, yield) and their impact on the learning performance at the system-level, using a device-algorithm co-design methodology. • Provides single-source reference to recent breakthroughs in resistive synaptic devices, not only at individual cell-level, but also at integrated array-level; • Includes detailed discussion of the peripheral circuits and array architecture design of the neuro-crossbar system; • Focuses on new experimental results that are likely to solve practical, artificial intelligent problems, such as image classification.
700 1# - AUTHOR 2
Author 2 Yu, Shimeng.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-319-54313-0
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
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-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2017.
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-- text
-- txt
-- rdacontent
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-- computer
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-- rdamedia
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-- online resource
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-- rdacarrier
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-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic circuits.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Microprocessors.
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computer architecture.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Electronic Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Processor Architectures.
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-- ZDB-2-ENG
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-- ZDB-2-SXE

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