Testing of Interposer-Based 2.5D Integrated Circuits (Record no. 81027)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03665nam a22005415i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-319-54714-5 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220801222653.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 170320s2017 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319547145 |
| -- | 978-3-319-54714-5 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Wang, Ran. |
| 245 10 - TITLE STATEMENT | |
| Title | Testing of Interposer-Based 2.5D Integrated Circuits |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2017. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XIV, 182 p. 118 illus., 102 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Introduction -- Pre-Bond Testing of the Silicon Interposer -- Post-Bond Scan-based Testing of Interposer Interconnects -- Test Architecture and Test-Path Scheduling -- Built-In Self-Test -- ExTest Scheduling and Optimization -- A Programmable Method for Low-Power Scan Shift in SoC Dies -- Conclusions.-. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Chakrabarty, Krishnendu. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-319-54714-5 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2017. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer architecture. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic design. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic Design. |
| 912 ## - | |
| -- | ZDB-2-ENG |
| 912 ## - | |
| -- | ZDB-2-SXE |
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