Transaction Processing on Modern Hardware (Record no. 84939)

000 -LEADER
fixed length control field 03971nam a22005175i 4500
001 - CONTROL NUMBER
control field 978-3-031-01870-1
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20240730163737.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 220601s2019 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN 9783031018701
-- 978-3-031-01870-1
082 04 - CLASSIFICATION NUMBER
Call Number 004.6
100 1# - AUTHOR NAME
Author Sadoghi, Mohammad.
245 10 - TITLE STATEMENT
Title Transaction Processing on Modern Hardware
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2019.
300 ## - PHYSICAL DESCRIPTION
Number of Pages XV, 122 p.
490 1# - SERIES STATEMENT
Series statement Synthesis Lectures on Data Management,
505 0# - FORMATTED CONTENTS NOTE
Remark 2 Introduction -- Transaction Concepts -- Multi-Version Concurrency Revisited -- Coordination-Avoidance Concurrency -- Novel Transactional System Architectures -- Hardware-Assisted Transactional Utilities -- Transactions on Heterogeneous Hardware -- Outlook: The Era of Hardware Specialization and Beyond -- Bibliography -- Authors' Biographies.
520 ## - SUMMARY, ETC.
Summary, etc The last decade has brought groundbreaking developments in transaction processing. This resurgence of an otherwise mature research area has spurred from the diminishing cost per GB of DRAM that allows many transaction processing workloads to be entirely memory-resident. This shift demanded a pause to fundamentally rethink the architecture of database systems. The data storage lexicon has now expanded beyond spinning disks and RAID levels to include the cache hierarchy, memory consistency models, cache coherence and write invalidation costs, NUMA regions, and coherence domains. New memory technologies promise fast non-volatile storage and expose unchartered trade-offs for transactional durability, such as exploiting byte-addressable hot and cold storage through persistent programming that promotes simpler recovery protocols. In the meantime, the plateauing single-threaded processor performance has brought massive concurrency within a single node, first in the form of multi-core, andnow with many-core and heterogeneous processors. The exciting possibility to reshape the storage, transaction, logging, and recovery layers of next-generation systems on emerging hardware have prompted the database research community to vigorously debate the trade-offs between specialized kernels that narrowly focus on transaction processing performance vs. designs that permit transactionally consistent data accesses from decision support and analytical workloads. In this book, we aim to classify and distill the new body of work on transaction processing that has surfaced in the last decade to navigate researchers and practitioners through this intricate research subject.
700 1# - AUTHOR 2
Author 2 Blanas, Spyros.
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier https://doi.org/10.1007/978-3-031-01870-1
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks
264 #1 -
-- Cham :
-- Springer International Publishing :
-- Imprint: Springer,
-- 2019.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computer networks .
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Data structures (Computer science).
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Information theory.
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Computer Communication Networks.
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1
-- Data Structures and Information Theory.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
-- 2153-5426
912 ## -
-- ZDB-2-SXSC

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