A Primer on Compression in the Memory Hierarchy (Record no. 85445)
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| 000 -LEADER | |
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| fixed length control field | 04175nam a22005295i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-031-01751-3 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240730164222.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 220601s2016 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783031017513 |
| -- | 978-3-031-01751-3 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Sardashti, Somayeh. |
| 245 12 - TITLE STATEMENT | |
| Title | A Primer on Compression in the Memory Hierarchy |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2016. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XVIII, 70 p. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Synthesis Lectures on Computer Architecture, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | List of Figures -- List of Tables -- Preface -- Acknowledgments -- Introduction -- Compression Algorithms -- Cache Compression -- Memory Compression -- Cache/Memory Link Compression -- Concluding Remarks -- References -- Authors' Biographies . |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This synthesis lecture presents the current state-of-the-art in applying low-latency, lossless hardware compression algorithms to cache, memory, and the memory/cache link. There are many non-trivial challenges that must be addressed to make data compression work well in this context. First, since compressed data must be decompressed before it can be accessed, decompression latency ends up on the critical memory access path. This imposes a significant constraint on the choice of compression algorithms. Second, while conventional memory systems store fixed-size entities like data types, cache blocks, and memory pages, these entities will suddenly vary in size in a memory system that employs compression. Dealing with variable size entities in a memory system using compression has a significant impact on the way caches are organized and how to manage the resources in main memory. We systematically discuss solutions in the open literature to these problems. Chapter 2 provides the foundations of data compression by first introducing the fundamental concept of value locality. We then introduce a taxonomy of compression algorithms and show how previously proposed algorithms fit within that logical framework. Chapter 3 discusses the different ways that cache memory systems can employ compression, focusing on the trade-offs between latency, capacity, and complexity of alternative ways to compact compressed cache blocks. Chapter 4 discusses issues in applying data compression to main memory and Chapter 5 covers techniques for compressing data on the cache-to-memory links. This book should help a skilled memory system designer understand the fundamental challenges in applying compression to the memory hierarchy and introduce him/her to the state-of-the-art techniques in addressing them. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Arelakis, Angelos. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Stenström, Per. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Wood, David A. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-031-01751-3 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2016. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
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| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer architecture. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 1935-3243 |
| 912 ## - | |
| -- | ZDB-2-SXSC |
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