High Performance Embedded Architectures and Compilers (Record no. 91041)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 05823nam a22006735i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-642-11515-8 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240730181719.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 100301s2010 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9783642115158 |
| -- | 978-3-642-11515-8 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-3-642-11515-8 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | QA76.6-76.66 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UM |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | COM051000 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UM |
| Source | thema |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 005.11 |
| Edition number | 23 |
| 245 10 - TITLE STATEMENT | |
| Title | High Performance Embedded Architectures and Compilers |
| Medium | [electronic resource] : |
| Remainder of title | 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings / |
| Statement of responsibility, etc. | edited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2010. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Berlin, Heidelberg : |
| Name of producer, publisher, distributor, manufacturer | Springer Berlin Heidelberg : |
| -- | Imprint: Springer, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2010. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XIII, 370 p. |
| Other physical details | online resource. |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Content type code | txt |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Media type code | c |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Carrier type code | cr |
| Source | rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS | |
| File type | text file |
| Encoding format | |
| Source | rda |
| 490 1# - SERIES STATEMENT | |
| Series statement | Theoretical Computer Science and General Issues, |
| International Standard Serial Number | 2512-2029 ; |
| Volume/sequential designation | 5952 |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Invited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload - Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | This book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer programming. |
| 9 (RLIN) | 4169 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer arithmetic and logic units. |
| 9 (RLIN) | 36750 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Microprocessors. |
| 9 (RLIN) | 125907 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer architecture. |
| 9 (RLIN) | 3513 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer input-output equipment. |
| 9 (RLIN) | 22942 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Logic design. |
| 9 (RLIN) | 3686 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer networks . |
| 9 (RLIN) | 31572 |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Programming Techniques. |
| 9 (RLIN) | 125908 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Arithmetic and Logic Structures. |
| 9 (RLIN) | 36752 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Processor Architectures. |
| 9 (RLIN) | 125909 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Input/Output and Data Communications. |
| 9 (RLIN) | 37326 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Logic Design. |
| 9 (RLIN) | 3686 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer Communication Networks. |
| 9 (RLIN) | 125910 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Patt, Yale N. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 125911 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Foglia, Pierfrancesco. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 125912 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Duesterwald, Evelyn. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 125913 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Faraboschi, Paolo. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 125914 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Martorell, Xavier. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 125915 |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 9 (RLIN) | 125916 |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer Nature eBook |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Printed edition: |
| International Standard Book Number | 9783642115141 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Printed edition: |
| International Standard Book Number | 9783642115165 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| Uniform title | Theoretical Computer Science and General Issues, |
| International Standard Serial Number | 2512-2029 ; |
| Volume/sequential designation | 5952 |
| 9 (RLIN) | 125917 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://doi.org/10.1007/978-3-642-11515-8">https://doi.org/10.1007/978-3-642-11515-8</a> |
| 912 ## - | |
| -- | ZDB-2-SCS |
| 912 ## - | |
| -- | ZDB-2-SXCS |
| 912 ## - | |
| -- | ZDB-2-LNC |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks-Lecture Notes in CS |
No items available.