Reconfigurable Computing: Architectures and Applications (Record no. 95336)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 08186nam a22006255i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-540-36863-2 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240730194823.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 100301s2006 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9783540368632 |
| -- | 978-3-540-36863-2 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/11802839 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | QA76.9.S88 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UYD |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | COM011000 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UYD |
| Source | thema |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004.2 |
| Edition number | 23 |
| 245 10 - TITLE STATEMENT | |
| Title | Reconfigurable Computing: Architectures and Applications |
| Medium | [electronic resource] : |
| Remainder of title | Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers / |
| Statement of responsibility, etc. | edited by Koen Bertels, João M.P. Cardoso, Stamatis Vassiliadis. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2006. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Berlin, Heidelberg : |
| Name of producer, publisher, distributor, manufacturer | Springer Berlin Heidelberg : |
| -- | Imprint: Springer, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2006. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XVI, 469 p. |
| Other physical details | online resource. |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Content type code | txt |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Media type code | c |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Carrier type code | cr |
| Source | rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS | |
| File type | text file |
| Encoding format | |
| Source | rda |
| 490 1# - SERIES STATEMENT | |
| Series statement | Theoretical Computer Science and General Issues, |
| International Standard Serial Number | 2512-2029 ; |
| Volume/sequential designation | 3985 |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Applications -- Implementation of Realtime and Highspeed Phase Detector on FPGA -- Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform -- Configurable Embedded Core for Controlling Electro-Mechanical Systems -- Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors -- Dynamic Partial Reconfigurable FIR Filter Design -- Event-Driven Simulation Engine for Spiking Neural Networks on a Chip -- Towards an Optimal Implementation of MLP in FPGA -- Power -- Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture -- Quality Driven Dynamic Low Power Reconfiguration of Handhelds -- An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects -- Image Processing -- Highly Paralellized Architecture for Image Motion Estimation -- Design Exploration of a Video Pre-processor for an FPGA Based SoC -- QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection -- Applications of Small-Scale Reconfigurability to Graphics Processors -- An Embedded Multi-camera System for Simultaneous Localization and Mapping -- Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor -- Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip -- Handel-C Design Enhancement for FPGA-Based DV Decoder -- Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform -- A New VLSI Architecture of Lifting-Based DWT -- Architecture Based on FPGA's for Real-Time Image Processing -- Real Time Image Processing on a Portable Aid Device for Low Vision Patients -- General Purpose Real-Time Image Segmentation System.-Organization and Architecture -- Implementation of LPM Address Generators on FPGAs -- Self Reconfiguring EPIC Soft Core Processors -- Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs -- Area/Performance Improvement of NoC Architectures -- Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array -- A Flexible Multi-port Caching Scheme for Reconfigurable Platforms -- Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support -- A Reconfigurable Data Cache for Adaptive Processors -- The Emergence of Non-von Neumann Processors -- Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server -- A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs -- A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI -- PISC: Polymorphic Instruction Set Computers -- Networks and Communication -- Generic Network Interfaces for Plug and Play NoC Based Architecture -- Providing QoS Guarantees in a NoC by Virtual Channel Reservation -- Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA -- A Reconfigurable Architecture for MIMO Square Root Decoder -- Security -- Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking -- Updates on the Security of FPGAs Against Power Analysis Attacks -- Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems -- FPGA Implementation of a GF(2 m ) Tate Pairing Architecture -- Iterative Modular Division over GF(2 m ): Novel Algorithm and Implementations on FPGA -- Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider -- UNITE: Uniform Hardware-BasedNetwork Intrusion deTection Engine -- Tools -- Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs -- Automatic Compilation Framework for Bloom Filter Based Intrusion Detection -- A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware -- Hardware and a Tool Chain for ADRES -- Integrating Custom Instruction Specifications into C Development Processes -- A Compiler-Oriented Architecture Description for Reconfigurable Systems -- Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility -- High-Level Synthesis Using SPARK and Systolic Array -- Super Semi-systolic Array-Based Application-Specific PLD Architecture. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | 1 The International Workshop on Recon?gurable Computing (ARC) started in 2005 in Algarve, Portugal. The major motivation was to create an event where on-going research e?orts as well as more elaborated, interesting and hi- quality work on applied recon?gurable computing could be presented and d- cussed. Over the last couple of years recon?gurable computing has become a we- known and established research area producing interesting as well as important results in both general and embedded computing systems. It is also getting more and more interest from industry which is attracted by the (design and development) ?exibility as well as the performance improvements that can be expected from this technology. As recon?gurablecomputing has blurred the gap between software and hardware, some even speak of a radical new programming paradigm opening a new realm of unseen applications and opportunities. The logo of the ARC workshop is the Nonius, a measurement instrument used in the Portuguese period of discoveries that was invented by Pedro Nunes, a Portuguesemathematician. As the logo suggests,the main motto of ARC is to help to navigate the world of recon?gurable computing. Driven by this motto, we hope ARC contributes to solid advances on recon?gurable computing. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer systems. |
| 9 (RLIN) | 158095 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computers. |
| 9 (RLIN) | 8172 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Microprocessors. |
| 9 (RLIN) | 158096 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer architecture. |
| 9 (RLIN) | 3513 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer networks . |
| 9 (RLIN) | 31572 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Electronic digital computers |
| General subdivision | Evaluation. |
| 9 (RLIN) | 21495 |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer System Implementation. |
| 9 (RLIN) | 38514 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer Hardware. |
| 9 (RLIN) | 33420 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Processor Architectures. |
| 9 (RLIN) | 158097 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer Communication Networks. |
| 9 (RLIN) | 158098 |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | System Performance and Evaluation. |
| 9 (RLIN) | 32047 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Bertels, Koen. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 158099 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Cardoso, João M.P. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 158100 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Vassiliadis, Stamatis. |
| Relator term | editor. |
| Relationship | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 9 (RLIN) | 158101 |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 9 (RLIN) | 158102 |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer Nature eBook |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Printed edition: |
| International Standard Book Number | 9783540367086 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Printed edition: |
| International Standard Book Number | 9783540826972 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| Uniform title | Theoretical Computer Science and General Issues, |
| International Standard Serial Number | 2512-2029 ; |
| Volume/sequential designation | 3985 |
| 9 (RLIN) | 158103 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://doi.org/10.1007/11802839">https://doi.org/10.1007/11802839</a> |
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| -- | ZDB-2-LNC |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks-Lecture Notes in CS |
No items available.