Introduction.- Continuous-Time Delta-Sigma Modulator.- Continuous-Time Delta-Sigma Modulators at High Sampling Rates -- A 4GHz Continuous-Time (SEV(B ADC -- A 2GHz Continuous-Time (SEV(B ADC with Dynamic Error Correction.- Conclusions -- Appendices.

This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital converters (ADCs) in nanometer-CMOS processes.  The authors offer a clear and complete picture of system level challenges and practical design solutions in high-speed Delta-Sigma modulators.  Readers will be enabled to implement ADCs as continuous-time delta-sigma (CT∆(SV(B) modulators, offering simple resistive inputs, which do not require the use of power-hungry input buffers, as well as offering inherent anti-aliasing, which simplifies system integration. The authors focus on the design of high speed and wide-bandwidth (SEV(BMs that make a step in bandwidth range which was previously only possible with Nyquist converters. More specifically, this book describes the stability, power efficiency, and linearity limits of (SEV(BMs, aiming at a GHz sampling frequency.   • Provides overview of trends in Wide Bandwidth and High Dynamic Range analog-to-digital converters (ADCs); • Enables the design of a wide bandwidth, high dynamic range modulator with state-of-the-art power efficiency; • Includes introduction to Continuous-Time Delta-Sigma Modulators and its system level modeling; • Explains issues relating to stability of Continuous-Time Delta-Sigma Modulators; • Includes discussion of system level non-idealities in Continuous-Time Delta-Sigma Modulators; • System level design of  CT∆(SV(B modulators at GHz sampling frequencies; • Practical implementation details of high speed CT∆(SV(B ADCs; • Overview of static and dynamic error correction techniques in ∆(SV(B ADCs; • Dynamic error correction techniques that are suitable for high speed CT∆(SV(B ADCs.