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Hardware Architectures for Post-Quantum Digital Signature Schemes [electronic resource] / by Deepraj Soni, Kanad Basu, Mohammed Nabeel, Najwa Aaraj, Marc Manzano, Ramesh Karri.

By: Soni, Deepraj [author.].
Contributor(s): Basu, Kanad [author.] | Nabeel, Mohammed [author.] | Aaraj, Najwa [author.] | Manzano, Marc [author.] | Karri, Ramesh [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookPublisher: Cham : Springer International Publishing : Imprint: Springer, 2021Edition: 1st ed. 2021.Description: XXII, 170 p. 68 illus., 66 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783030576820.Subject(s): Electronic circuits | Cooperating objects (Computer systems) | Microprocessors | Computer architecture | Electronic Circuits and Systems | Cyber-Physical Systems | Processor ArchitecturesAdditional physical formats: Printed edition:: No title; Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Introduction -- qTESLA -- CRYSTALS –Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions.
In: Springer Nature eBookSummary: This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels.
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Introduction -- qTESLA -- CRYSTALS –Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions.

This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels.

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