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A Synergistic Framework for Hardware IP Privacy and Integrity Protection [electronic resource] / by Meng Li, David Z. Pan.

By: Li, Meng [author.].
Contributor(s): Pan, David Z [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookPublisher: Cham : Springer International Publishing : Imprint: Springer, 2020Edition: 1st ed. 2020.Description: IX, 139 p. 74 illus., 67 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783030412470.Subject(s): Electronic circuits | Cooperating objects (Computer systems) | Microprocessors | Computer architecture | Electronic Circuits and Systems | Cyber-Physical Systems | Processor ArchitecturesAdditional physical formats: Printed edition:: No title; Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Introduction -- Practical Split Manufacturing Optimization -- IC Camouflaging Optimization and Evaluation -- Fault Attack Protection and Evaluation -- Conclusion.
In: Springer Nature eBookSummary: This book proposes a synergistic framework to help IP vendors to protect hardware IP privacy and integrity from design, optimization, and evaluation perspectives. The proposed framework consists of five interacting components that directly target at the primary IP violations. All the five algorithms are developed based on rigorous mathematical modeling for primary IP violations and focus on different stages of IC design, which can be combined to provide a formal security guarantee.
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Introduction -- Practical Split Manufacturing Optimization -- IC Camouflaging Optimization and Evaluation -- Fault Attack Protection and Evaluation -- Conclusion.

This book proposes a synergistic framework to help IP vendors to protect hardware IP privacy and integrity from design, optimization, and evaluation perspectives. The proposed framework consists of five interacting components that directly target at the primary IP violations. All the five algorithms are developed based on rigorous mathematical modeling for primary IP violations and focus on different stages of IC design, which can be combined to provide a formal security guarantee.

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