Central Library

Normal view MARC view ISBD view

Low-Power Design and Power-Aware Verification [electronic resource] / by Progyna Khondkar.

By: Khondkar, Progyna [author.].
Contributor(s): SpringerLink (Online service).
Material type: materialTypeLabelBookPublisher: Cham : Springer International Publishing : Imprint: Springer, 2018Edition: 1st ed. 2018.Description: XV, 155 p. 19 illus., 12 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783319666198.Subject(s): Electronic circuits | Software engineering | Microprocessors | Computer architecture | Computers | Electronic Circuits and Systems | Software Engineering | Processor Architectures | Hardware Performance and ReliabilityAdditional physical formats: Printed edition:: No title; Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References. .
In: Springer Nature eBookSummary: Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers. .
    average rating: 0.0 (0 votes)
No physical items for this record

1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References. .

Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers. .

There are no comments for this item.

Log in to your account to post a comment.