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Separation Logic for High-level Synthesis [electronic resource] / by Felix Winterstein.

By: Winterstein, Felix [author.].
Contributor(s): SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Springer Theses, Recognizing Outstanding Ph.D. Research: Publisher: Cham : Springer International Publishing : Imprint: Springer, 2017Edition: 1st ed. 2017.Description: XIX, 132 p. 19 illus., 7 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783319532226.Subject(s): Electronic circuits | Computer storage devices | Memory management (Computer science) | Logic design | Compilers (Computer programs) | Electronic Circuits and Systems | Computer Memory Structure | Logic Design | Compilers and InterpretersAdditional physical formats: Printed edition:: No title; Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
1. Introduction -- 2. High-level Synthesis of Dynamic Data Structures -- 3. Background -- 4. Heap Partitioning and Parallelisation -- 5. Custom Multi-Cache Architectures -- 6. Conclusion -- Bibliography -- Appendices.
In: Springer Nature eBookSummary: This book presents novel compiler techniques, which combine a rigorous mathematical framework, novel program analyses and digital hardware design to advance current high-level synthesis tools and extend their scope beyond the industrial ‘state of the art’. Implementing computation on customised digital hardware plays an increasingly important role in the quest for energy-efficient high-performance computing. Field-programmable gate arrays (FPGAs) gain efficiency by encoding the computing task into the chip’s physical circuitry and are gaining rapidly increasing importance in the processor market, especially after recent announcements of large-scale deployments in the data centre. This is driving, more than ever, the demand for higher design entry abstraction levels, such as the automatic circuit synthesis from high-level languages (high-level synthesis). The techniques in this book apply formal reasoning to high-level synthesis in the context of demonstrably practical applications.<.
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1. Introduction -- 2. High-level Synthesis of Dynamic Data Structures -- 3. Background -- 4. Heap Partitioning and Parallelisation -- 5. Custom Multi-Cache Architectures -- 6. Conclusion -- Bibliography -- Appendices.

This book presents novel compiler techniques, which combine a rigorous mathematical framework, novel program analyses and digital hardware design to advance current high-level synthesis tools and extend their scope beyond the industrial ‘state of the art’. Implementing computation on customised digital hardware plays an increasingly important role in the quest for energy-efficient high-performance computing. Field-programmable gate arrays (FPGAs) gain efficiency by encoding the computing task into the chip’s physical circuitry and are gaining rapidly increasing importance in the processor market, especially after recent announcements of large-scale deployments in the data centre. This is driving, more than ever, the demand for higher design entry abstraction levels, such as the automatic circuit synthesis from high-level languages (high-level synthesis). The techniques in this book apply formal reasoning to high-level synthesis in the context of demonstrably practical applications.<.

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