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High Performance Embedded Architectures and Compilers [electronic resource] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer.

Contributor(s): De Bosschere, Koen [editor.] | Kaeli, David [editor.] | Stenström, Per [editor.] | Whalley, David [editor.] | Ungerer, Theo [editor.] | SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Theoretical Computer Science and General Issues: 4367Publisher: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2007Edition: 1st ed. 2007.Description: XI, 307 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783540693383.Subject(s): Computer science | Computer arithmetic and logic units | Microprocessors | Computer architecture | Computer input-output equipment | Logic design | Computer networks  | Theory of Computation | Arithmetic and Logic Structures | Processor Architectures | Input/Output and Data Communications | Logic Design | Computer Communication NetworksAdditional physical formats: Printed edition:: No title; Printed edition:: No titleDDC classification: 004.0151 Online resources: Click here to access online
Contents:
Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints.
In: Springer Nature eBook
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Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints.

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