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Reconfigurable Computing: Architectures, Tools and Applications [electronic resource] : 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013, Proceedings / edited by Philip Brisk, José Gabriel de Figueiredo Coutinho, Pedro Diniz.

Contributor(s): Brisk, Philip [editor.] | de Figueiredo Coutinho, José Gabriel [editor.] | Diniz, Pedro [editor.] | SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Theoretical Computer Science and General Issues: 7806Publisher: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2013Edition: 1st ed. 2013.Description: XVI, 238 p. 104 illus. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783642368127.Subject(s): Computers | Computer engineering | Computer networks  | Algorithms | Computer Hardware | Computer Engineering and Networks | AlgorithmsAdditional physical formats: Printed edition:: No title; Printed edition:: No titleDDC classification: 004 Online resources: Click here to access online
Contents:
Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications -- Hardware Acceleration of Genetic Sequence Alignment -- An FPGA Acceleration for the Kd-tree Search in Photon Mapping -- SEU Resilience of DES, AES in SRAM-based FPGA -- An Architecture for IPv6 Lookup Using Parallel Index Generation Units -- Hardware Index to Set Partition Converter -- Teaching SoC Using Video Games to Improve Student Engagement -- Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-based Custom Computing -- Hardware Acceleration of Matrix Multiplication Over Small Prime Finite Fields -- Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms -- Architecture for Transparent Binary Acceleration of Loops with Memory Accesses -- Parametric Optimization of Reconfigurable Designs using Machine Learning -- Fast Template-based Heterogeneous MPSoC Synthesis on FPGA -- Hierarchical and Multiple Switching NoC with Floorplan based Adaptability -- Performance Analysis And Optimization of High Density Tree-Based 3D Multilevel FPGA.
In: Springer Nature eBookSummary: This book constitutes the thoroughly refereed conference proceedings of the 9th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2013, held in Los Angeles, CA, USA, in March 2013. The 28 revised papers presented, consisting of 20 full papers and 11 poster papers were carefully selected from 41 submissions. The topics covered are applications, arithmetic, design optimization for FPGAs, architectures, place and routing.
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Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications -- Hardware Acceleration of Genetic Sequence Alignment -- An FPGA Acceleration for the Kd-tree Search in Photon Mapping -- SEU Resilience of DES, AES in SRAM-based FPGA -- An Architecture for IPv6 Lookup Using Parallel Index Generation Units -- Hardware Index to Set Partition Converter -- Teaching SoC Using Video Games to Improve Student Engagement -- Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-based Custom Computing -- Hardware Acceleration of Matrix Multiplication Over Small Prime Finite Fields -- Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms -- Architecture for Transparent Binary Acceleration of Loops with Memory Accesses -- Parametric Optimization of Reconfigurable Designs using Machine Learning -- Fast Template-based Heterogeneous MPSoC Synthesis on FPGA -- Hierarchical and Multiple Switching NoC with Floorplan based Adaptability -- Performance Analysis And Optimization of High Density Tree-Based 3D Multilevel FPGA.

This book constitutes the thoroughly refereed conference proceedings of the 9th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2013, held in Los Angeles, CA, USA, in March 2013. The 28 revised papers presented, consisting of 20 full papers and 11 poster papers were carefully selected from 41 submissions. The topics covered are applications, arithmetic, design optimization for FPGAs, architectures, place and routing.

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