Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces :  high performance compute and system-in-package / 
edited by Beth Keser, Steffen Kröhnert. 
 - 1 online resource (323 pages). 
 - IEEE Press series .
 - IEEE Press series. .
<br/><br/> Discover an up-to-date exploration of Embedded and Fan-Out Waver and Panel Level technologies In Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package , a team of accomplished semiconductor experts delivers an in-depth treatment of various fan-out and embedded die approaches. The book begins with a market analysis of the latest technology trends in Fan-Out and Wafer Level Packaging before moving on to a cost analysis of these solutions. The contributors discuss the new package types for advanced application spaces being created by companies like TSMC, Deca Technologies, and ASE Group. Finally, emerging technologies from academia are explored. Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces is an indispensable resource for microelectronic package engineers, managers, and decision makers working with OEMs and IDMs. It is also a must-read for professors and graduate students working in microelectronics packaging research. 
<br/><br/><label>ISBN: </label>9781119793847 111979384X 9781119793892 1119793890 9781119793908 1119793904 
<br/><br/><label>Standard No.: </label>10.1002/9781119793908  doi 
<br/><br/><label>Source: </label>9648539  IEEE 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Microelectronic packaging.<br/>Microelectronic packaging.
<br/><br/><label>Index Terms--Genre/Form: </label><br/>Electronic books.
<br/><br/><label>LC Class. No.: </label>TK7870.15  / .E43 2021 
<br/><br/><label>Dewey Class. No.: </label>621.381/046