Rahimi, Abbas. <br/><br/>
From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators  [electronic resource] / 
by Abbas Rahimi, Luca Benini, Rajesh K. Gupta. 
 - 1st ed. 2017. 
 - XV, 197 p. 86 illus., 48 illus. in color.  online resource. 
<br/><br/>Introduction -- Part 1. Predicting and Preventing Errors -- Instruction-Level Tolerance -- Sequence-Level Tolerance -- Procedure-Level Tolerance -- Kernel-Level Tolerance -- Hierarchically Focused Guardbanding -- Part 2. Detecting and Correcting Errors -- Work-Unit Tolerance -- Memristive-Based Associative Memory for Error Recovery -- Part 3. Accepting Errors -- Accuracy-Configurable OpenMP -- An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration -- Memristive-Based Associative Memory for Approximate Computational Reuse -- Spatial and Temporal Memoization -- Outlook. 
<br/><br/> This book focuses on computing devices and their design at various levels to combat variability. The authors provide a review of key concepts with particular emphasis on timing errors caused by various variability sources. They discuss methods to predict and prevent, detect and correct, and finally conditions under which such errors can be accepted; they also consider their implications on cost, performance and quality. Coverage includes a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software. These can be combined in various ways to achieve specific goals related to observability and controllability of the variability effects, providing means to achieve cross layer or hybrid resilience. · Covers challenges and opportunities in identifying microelectronic variability and the resulting errors at various layers in the system abstraction; · Enables readers to assess how various levels of circuit and system design can mitigate the effects of variability; · Demonstrates overall system architecture of what is now called “approximate computing” paradigm in massively parallel integrated architectures and accelerators. 
<br/><br/><label>ISBN: </label>9783319537689 
<br/><br/><label>Standard No.: </label>10.1007/978-3-319-53768-9  doi 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Electronic circuits.<br/>Microprocessors.<br/>Computer architecture.<br/>Logic design.<br/>Electronic Circuits and Systems.<br/>Processor Architectures.<br/>Logic Design.
<br/><br/><label>LC Class. No.: </label>TK7867-7867.5 
<br/><br/><label>Dewey Class. No.: </label>621.3815