Wang, Zheng. <br/><br/>
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip  [electronic resource] / 
by Zheng Wang, Anupam Chattopadhyay. 
 - 1st ed. 2018. 
 - XX, 197 p. 104 illus., 72 illus. in color.  online resource. 
 - Computer Architecture and Design Methodologies,  2367-3486 .
 - Computer Architecture and Design Methodologies, .
<br/><br/>Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook. 
<br/><br/> This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. . 
<br/><br/><label>ISBN: </label>9789811010736 
<br/><br/><label>Standard No.: </label>10.1007/978-981-10-1073-6  doi 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Electronic circuits.<br/>Computers.<br/>Electronic Circuits and Systems.<br/>Hardware Performance and Reliability.
<br/><br/><label>LC Class. No.: </label>TK7867-7867.5 
<br/><br/><label>Dewey Class. No.: </label>621.3815