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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip [electronic resource] / by Zheng Wang, Anupam Chattopadhyay.

By: Wang, Zheng [author.].
Contributor(s): Chattopadhyay, Anupam [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Computer Architecture and Design Methodologies: Publisher: Singapore : Springer Nature Singapore : Imprint: Springer, 2018Edition: 1st ed. 2018.Description: XX, 197 p. 104 illus., 72 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9789811010736.Subject(s): Electronic circuits | Computers | Electronic Circuits and Systems | Hardware Performance and ReliabilityAdditional physical formats: Printed edition:: No title; Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.
In: Springer Nature eBookSummary: This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .
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Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .

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