000 03660nam a22005055i 4500
001 978-3-319-22035-2
003 DE-He213
005 20200420221255.0
007 cr nn 008mamaa
008 150827s2016 gw | s |||| 0|eng d
020 _a9783319220352
_9978-3-319-22035-2
024 7 _a10.1007/978-3-319-22035-2
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aMohamed, Khaled Salah.
_eauthor.
245 1 0 _aIP Cores Design from Specifications to Production
_h[electronic resource] :
_bModeling, Verification, Optimization, and Protection /
_cby Khaled Salah Mohamed.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2016.
300 _aIX, 154 p. 153 illus., 115 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aAnalog Circuits and Signal Processing,
_x1872-082X
505 0 _a1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions.
520 _aThis book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including  those associated with many of the most common memory cores, controller IPs  and system-on-chip (SoC) buses. Readers will also benefit from the author's practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.  A SoC case study is presented to compare traditional verification with the new verification methodologies. �         Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; �         Introduce a deep introduction for Verilog for both implementation and verification point of view.  �         Demonstrates how to use IP in applications such as memory controllers and SoC buses. �         Describes a new verification methodology called bug localization; �         Presents a novel scan-chain methodology for RTL debugging; �         Enables readers to employ UVM methodology in straightforward, practical terms.
650 0 _aEngineering.
650 0 _aMicroprocessors.
650 0 _aElectronics.
650 0 _aMicroelectronics.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aProcessor Architectures.
650 2 4 _aElectronics and Microelectronics, Instrumentation.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783319220345
830 0 _aAnalog Circuits and Signal Processing,
_x1872-082X
856 4 0 _uhttp://dx.doi.org/10.1007/978-3-319-22035-2
912 _aZDB-2-ENG
942 _cEBK
999 _c52840
_d52840