000 | 03305nam a22005055i 4500 | ||
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001 | 978-3-319-25766-2 | ||
003 | DE-He213 | ||
005 | 20200421111159.0 | ||
007 | cr nn 008mamaa | ||
008 | 151216s2015 gw | s |||| 0|eng d | ||
020 |
_a9783319257662 _9978-3-319-25766-2 |
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024 | 7 |
_a10.1007/978-3-319-25766-2 _2doi |
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050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
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072 | 7 |
_aTEC008010 _2bisacsh |
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082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aEzz-Eldin, Rabab. _eauthor. |
|
245 | 1 | 0 |
_aAnalysis and Design of Networks-on-Chip Under High Process Variation _h[electronic resource] / _cby Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed. |
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2015. |
|
300 |
_aXXI, 141 p. 84 illus., 34 illus. in color. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _aIntroduction -- Network On Chip Aspects -- Interconnection -- Process Variation -- Synchronous And Asynchronous NoC Design Under High Process Variation -- Novel Routing Algorithm -- Simulation Results -- Conclusions. | |
520 | _aThis book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. Demonstrates the impact of process variation on Networks-on-Chip of different topologies; Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms; Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appr opriate output path based on process variation and congestion. | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aMicroprocessors. | |
650 | 0 | _aElectronics. | |
650 | 0 | _aMicroelectronics. | |
650 | 0 | _aElectronic circuits. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aProcessor Architectures. |
650 | 2 | 4 | _aElectronics and Microelectronics, Instrumentation. |
700 | 1 |
_aEl-Moursy, Magdy Ali. _eauthor. |
|
700 | 1 |
_aHamed, Hesham F. A. _eauthor. |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9783319257648 |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-3-319-25766-2 |
912 | _aZDB-2-ENG | ||
942 | _cEBK | ||
999 |
_c53690 _d53690 |