000			03401nam a22004815i 4500
001			978-3-319-10569-7
003			DE-He213
005			20200421111836.0
007			cr nn 008mamaa
008			141030s2015 gw | s |||| 0|eng d
020			_a9783319105697 _9978-3-319-10569-7
024	7		_a10.1007/978-3-319-10569-7 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
245	1	0	_aAdvanced Hardware Design for Error Correcting Codes _h[electronic resource] / _cedited by Cyrille Chavet, Philippe Coussy.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2015.
300			_aIX, 192 p. 81 illus., 25 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aUser Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey.                                                                                                                                       .
520			_aThis book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book's chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.
650		0	_aEngineering.
650		0	_aComputers.
650		0	_aElectrical engineering.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aCommunications Engineering, Networks.
650	2	4	_aInformation Systems and Communication Service.
700	1		_aChavet, Cyrille. _eeditor.
700	1		_aCoussy, Philippe. _eeditor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783319105680
856	4	0	_uhttp://dx.doi.org/10.1007/978-3-319-10569-7
912			_aZDB-2-ENG
942			_cEBK
999			_c55290 _d55290