000 03745nam a22004815i 4500
001 978-3-319-01150-9
003 DE-He213
005 20200421112039.0
007 cr nn 008mamaa
008 130906s2014 gw | s |||| 0|eng d
020 _a9783319011509
_9978-3-319-01150-9
024 7 _a10.1007/978-3-319-01150-9
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aJamin, Olivier.
_eauthor.
245 1 0 _aBroadband Direct RF Digitization Receivers
_h[electronic resource] /
_cby Olivier Jamin.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2014.
300 _aXVI, 162 p. 166 illus., 68 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aAnalog Circuits and Signal Processing,
_x1872-082X ;
_v121
505 0 _aRF Receiver Architecture State-of-the-Art -- System-Level Design Framework for Direct RF Digitization Receivers -- Application to the System Design of a Multi-Channel Cable Receiver -- Realization & Measurements -- Conclusions & Perspectives.
520 _aThis book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains.  A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level analysis.  Special focus is given to noise analysis (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion analysis, including the impact of the sampling strategy (low-pass, band-pass), analysis of time-interleaved ADC channel mismatches, sampling clock purity and digital channel selection. The system-level framework described is applied to the design of a cable multi-channel RF direct digitization receiver. An optimum RF signal conditioning, and some algorithms (automatic gain control loop, RF front-end amplitude equalization control loop) are used to relax the requirements of a 2.7GHz 11-bit ADC. A two-chip implementation is presented, using BiCMOS and 65nm CMOS processes, together with the block and system-level measurement results. Readers will benefit from the techniques presented, which are highly competitive, both in terms of cost and RF performance, while drastically reducing power consumption.  �         Provides system-level analysis of direct RF sampling & digitization receivers, from the antenna to the digital channel selection; �         Includes analysis of broadband non-linearity, applicable for low-pass and band-pass sampling strategies; Describes system-level design of an application-optimized signal conditioner, including a single-inductance multi-slope programmable RF amplitude equalizer, together with its control algorithm and a mixed-signal AGC loop combining RMS and peak detection.  .
650 0 _aEngineering.
650 0 _aMicroprocessors.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aSignal, Image and Speech Processing.
650 2 4 _aProcessor Architectures.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783319011493
830 0 _aAnalog Circuits and Signal Processing,
_x1872-082X ;
_v121
856 4 0 _uhttp://dx.doi.org/10.1007/978-3-319-01150-9
912 _aZDB-2-ENG
942 _cEBK
999 _c56535
_d56535