000 04180nam a22005175i 4500
001 978-81-322-2508-9
003 DE-He213
005 20200421112221.0
007 cr nn 008mamaa
008 150805s2016 ii | s |||| 0|eng d
020 _a9788132225089
_9978-81-322-2508-9
024 7 _a10.1007/978-81-322-2508-9
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
245 1 0 _aFundamentals of Bias Temperature Instability in MOS Transistors
_h[electronic resource] :
_bCharacterization Methods, Process and Materials Impact, DC and AC Modeling /
_cedited by Souvik Mahapatra.
250 _a1st ed. 2015.
264 1 _aNew Delhi :
_bSpringer India :
_bImprint: Springer,
_c2016.
300 _aXVI, 269 p. 201 illus., 67 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSpringer Series in Advanced Microelectronics,
_x1437-0387 ;
_v52
505 0 _aIntroduction: Bias Temperature Instability (BTI) in N and P Channel MOSFETs -- Characterization Methods for BTI Degradation and Associated Gate Insulator Defects -- Physical Mechanism of BTI Degradation - Direct Estimation of Trap Generation and Trapping -- Physical Mechanism of BTI Degradation -Modeling of Process and Material Dependence -- Reaction-Diffusion Model -- Modeling of DC and AC NBTI Degradation and Recovery for SiON and HKMG MOSFETs -- Index.
520 _aThis book aims to cover different aspects of Bias Temperature Instability (BTI). BTI remains as an important reliability concern for CMOS transistors and circuits. Development of BTI resilient technology relies on utilizing artefact-free stress and measurement methods and suitable physics-based models for accurate determination of degradation at end-of-life, and understanding the gate insulator process impact on BTI. This book discusses different ultra-fast characterization techniques for recovery artefact free BTI measurements. It also covers different direct measurements techniques to access pre-existing and newly generated gate insulator traps responsible for BTI. The book provides a consistent physical framework for NBTI and PBTI respectively for p- and n- channel MOSFETs, consisting of trap generation and trapping. A physics-based compact model is presented to estimate measured BTI degradation in planar Si MOSFETs having differently processed SiON and HKMG gate insulators, in planar SiGe MOSFETs and also in Si FinFETs.  The contents also include a detailed investigation of the gate insulator process dependence of BTI in differently processed SiON and HKMG MOSFETs. The book then goes on to discuss Reaction-Diffusion (RD) model to estimate generation of new traps for DC and AC NBTI stress, and Transient Trap Occupancy Model (TTOM) to estimate charge occupancy of generated traps and their contribution to BTI degradation. Finally, a comprehensive NBTI modeling framework including TTOM enabled RD model and hole trapping to predict time evolution of BTI degradation and recovery during and after DC stress for different stress and recovery biases and temperature, during consecutive arbitrary stress and recovery cycles, and during AC stress at different frequency and duty cycle. The contents of this book should prove useful to academia and professionals alike.
650 0 _aEngineering.
650 0 _aSolid state physics.
650 0 _aElectronics.
650 0 _aMicroelectronics.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aElectronics and Microelectronics, Instrumentation.
650 2 4 _aSolid State Physics.
700 1 _aMahapatra, Souvik.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9788132225072
830 0 _aSpringer Series in Advanced Microelectronics,
_x1437-0387 ;
_v52
856 4 0 _uhttp://dx.doi.org/10.1007/978-81-322-2508-9
912 _aZDB-2-ENG
942 _cEBK
999 _c57382
_d57382