000			03786nam a22005295i 4500
001			978-1-4614-4963-8
003			DE-He213
005			20200421112225.0
007			cr nn 008mamaa
008			130906s2014 xxu| s |||| 0|eng d
020			_a9781461449638 _9978-1-4614-4963-8
024	7		_a10.1007/978-1-4614-4963-8 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aOh, Taehyoun. _eauthor.
245	1	0	_aHigh Performance Multi-Channel High-Speed I/O Circuits _h[electronic resource] / _cby Taehyoun Oh, Ramesh Harjani.
264		1	_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2014.
300			_aX, 89 p. 64 illus., 44 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aAnalog Circuits and Signal Processing, _x1872-082X
505	0		_aIntroduction -- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process -- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process -- Adaptive XTCR, AGC, and Adaptive DFE Loop -- Research Summary & Contributions -- References -- Appendix A: Noise Analysis -- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os (≥ 4) -- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter -- Appendix D: Line Mismatch Sensitivity -- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench -- Appendix F: Bandwidth Improvement by Technology Scaling.
520			_aThis book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds.  This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures. �         Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits; �         Includes critical background knowledge related to channel ISI equalization circuits; �         Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems.
650		0	_aEngineering.
650		0	_aMicrowaves.
650		0	_aOptical engineering.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aMicrowaves, RF and Optical Engineering.
700	1		_aHarjani, Ramesh. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781461449621
830		0	_aAnalog Circuits and Signal Processing, _x1872-082X
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4614-4963-8
912			_aZDB-2-ENG
942			_cEBK
999			_c57627 _d57627