000			06175nam a2200949 i 4500
001			5676102
003			IEEE
005			20200421114119.0
006			m o d
007			cr |n|||||||||
008			151221s2010 njua ob 001 eng d
010			_z 2009049311 (print)
016			_z 015478740 (print)
020			_a9780470823798 _qebook
020			_z9780470823774 _qcloth
020			_z0470823771 _qcloth
024	7		_a10.1002/9780470823798 _2doi
035			_a(CaBNVSL)mat05676102
035			_a(IDAMS)0b0000648144b7d1
040			_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL
050		4	_aT385 _b.M62193 2010eb
082	0	0	_a621.3815 _222
245	0	0	_aMobile 3D graphics SoC : _bfrom algorithm to chip / _cJeong-Ho Woo ... [et al.].
246	3		_aMobile three-dimensional graphics systems on a chip
264		1	_aSingapore ; _bJohn Wiley & Sons, _cc2010.
264		2	_a[Piscataqay, New Jersey] : _bIEEE Xplore, _c[2010]
300			_a1 PDF (x, 327 pages) : _billustrations (some color).
336			_atext _2rdacontent
337			_aelectronic _2isbdmedia
338			_aonline resource _2rdacarrier
504			_aIncludes bibliographical references and index.
505	0		_aPreface -- 1 Introduction -- 1.1 Mobile 3D Graphics -- 1.2 Mobile Devices and Design Challenges -- 1.2.1 Mobile Computing Power -- 1.2.2 Mobile Display Devices -- 1.2.3 Design Challenges -- 1.3 Introduction to SoC Design -- 1.4 About this Book -- 2 Application Platform -- 2.1 SoC Design Paradigms -- 2.1.1 Platform and Set-based Design -- 2.1.2 Modeling: Memory and Operations -- 2.2 System Architecture -- 2.2.1 Reference Machine and API -- 2.2.2 Communication Architecture Design -- 2.2.3 System Analysis -- 2.3 Low-power SoC Design -- 2.3.1 CMOS Circuit-level Low-power Design -- 2.3.2 Architecture-level Low-power Design -- 2.3.3 System-level Low-power Design -- 2.4 Network-on-Chip based SoC -- 2.4.1 Network-on-Chip Basics -- 2.4.2 NoC Design Considerations -- 2.4.3 Case Studies of Chip Implementation -- 3 Introduction to 3D Graphics -- 3.1 The 3D Graphics Pipeline -- 3.1.1 The Application Stage -- 3.1.2 The Geometry Stage -- 3.1.3 The Rendering Stage -- 3.2 Programmable 3D Graphics -- 3.2.1 Programmable Graphics Pipeline -- 3.2.2 Shader Models -- 4 Mobile 3D Graphics -- 4.1 Principles of Mobile 3D Graphics -- 4.1.1 Application Challenges -- 4.1.2 Design Principles -- 4.2 Mobile 3D Graphics APIs -- 4.2.1 KAIST MobileGL -- 4.2.2 Khronos OpenGL-ES -- 4.2.3 Microsoft's Direct3D-Mobile -- 4.3 Summary and Future Directions -- 5 Mobile 3D Graphics SoC -- 5.1 Low-power Rendering Processor -- 5.1.1 Early Depth Test -- 5.1.2 Logarithmic Datapaths -- 5.1.3 Low-power Texture Unit -- 5.1.4 Tile-based Rendering -- 5.1.5 Texture Compression -- 5.1.6 Texture Filtering and Anti-aliasing -- 5.2 Low-power Shader -- 5.2.1 Vertex Cache -- 5.2.2 Low-power Register File -- 5.2.3 Mobile Unified Shader -- 6 Real Chip Implementations -- 6.1 KAIST RAMP Architecture -- 6.1.1 RAMP-IV -- 6.1.2 RAMP-V -- 6.1.3 RAMP-VI -- 6.1.4 RAMP-VII -- 6.2 Industry Architecture -- 6.2.1 nVidia Mobile GPU - SC10 and Tegra -- 6.2.2 Sony PSP -- 6.2.3 Imagination Technology MBX/SGX -- 7 Low-power Rasterizer Design.
505	8		_a7.1 Target System Architecture -- 7.2 Summary of Performance and Features -- 7.3 Block Diagram of the Rasterizer -- 7.4 Instruction Set Architecture (ISA) -- 7.5 Detailed Design with Register Transfer Level Code -- 7.5.1 Rasterization Top Block -- 7.5.2 Pipeline Architecture -- 7.5.3 Main Controller Design -- 7.5.4 Rasterization Core Unit -- 8 The Future of Mobile 3D Graphics -- 8.1 Game and Mapping Applications Involving Networking -- 8.2 Moves Towards More User-centered Applications -- 8.3 Final Remarks -- Appendix Verilog HDL Design -- A.1 Introduction to Verilog Design -- A.2 Design Level -- A.2.1 Behavior Level -- A.2.2 Register Transfer Level -- A.2.3 Gate Level -- A.3 Design Flow -- A.3.1 Specification -- A.3.2 High-level Design -- A.3.3 Low-level Design -- A.3.4 RTL Coding -- A.3.5 Simulation -- A.3.6 Synthesis -- A.3.7 Placement and Routing -- A.4 Verilog Syntax -- A.4.1 Modules -- A.4.2 Logic Values and Numbers -- A.4.3 Data Types -- A.4.4 Operators -- A.4.5 Assignment -- A.4.6 Ports and Connections -- A.4.7 Expressions -- A.4.8 Instantiation -- A.4.9 Miscellaneous -- A.5 Example of Four-bit Adder with Zero Detection -- A.6 Synthesis Scripts -- Glossaries -- Index.
506	1		_aRestricted to subscribers or individual electronic text purchasers.
530			_aAlso available in print.
538			_aMode of access: World Wide Web
588			_aDescription based on PDF viewed 12/21/2015.
650		0	_aComputer graphics.
650		0	_aMobile computing.
650		0	_aSystems on a chip.
650		0	_aThree-dimensional display systems.
655		0	_aElectronic books.
695			_aAlgorithm design and analysis
695			_aAsia
695			_aBandwidth
695			_aCognition
695			_aComputer architecture
695			_aDigital systems
695			_aGames
695			_aGeometry
695			_aGraphics
695			_aGraphics processing unit
695			_aHardware
695			_aHardware design languages
695			_aIndexes
695			_aLight sources
695			_aLighting
695			_aLogic gates
695			_aMemory management
695			_aMicroprocessors
695			_aMobile communication
695			_aMobile computing
695			_aMobile handsets
695			_aMultimedia communication
695			_aPipelines
695			_aPixel
695			_aPower demand
695			_aRandom access memory
695			_aRegisters
695			_aRendering (computer graphics)
695			_aSoftware
695			_aSolid modeling
695			_aSystem-on-a-chip
695			_aTerminology
695			_aThree dimensional displays
700	1		_aWoo, Jeong-Ho.
710	2		_aIEEE Xplore (Online Service), _edistributor.
710	2		_aJohn Wiley & Sons, _epublisher.
776	0	8	_iPrint version: _z9780470823774
856	4	2	_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5676102
942			_cEBK
999			_c59666 _d59666