000 02048cam a2200337Ii 4500
001 9781315191089
008 180417s2017 flu b ob 001 0 eng d
020 _a9781315191089
_q(e-book : PDF)
020 _a9781351751025
_q(e-book: Mobi)
020 _a9781351751049
_q(e-book: PDF)
020 _z9781498783590
_q(hardback)
024 7 _a10.1201/9781315191089
_2doi
035 _a(OCoLC)992167435
050 4 _aTK7871.95
082 0 4 _a621.3815/284
_223
100 1 _aDasgupta, Sudeb,
_eauthor.
_917414
245 1 0 _aSpacer engineered FinFET architectures :
_bhigh-performance digital circuit applicators /
_cby Sudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal.
250 _aFirst edition.
264 1 _aBoca Raton, FL :
_bRoutledge, an imprint of Taylor and Francis,
_c2017.
300 _a1 online resource (138 pages) :
_b49 illustrations
505 0 0 _achapter 1 Introduction to Nanoelectronics -- chapter 2 Tri-Gate FinFET Technology and Its Advancement -- chapter 3 Dual-k Spacer Device Architecture and Its Electrostatics -- chapter 4 Capacitive Analysis and Dual-k FinFET-Based Digital Circuit Design -- chapter 5 Design Metric Improvement of a Dual-k Based SRAM Cell -- chapter 6 Statistical Variability and Sensitivity Analysis.
520 3 _aThis book focusses on the spacer engineering aspects of novel MOS-based device circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.
650 0 _aMetal oxide semiconductor field-effect transistors.
_915501
650 0 _aSilicon-on-insulator technology.
_99843
700 1 _aKaushik, Brajesh Kumar,
_eauthor.
_917415
700 1 _aPal, Pankaj Kumar,
_eauthor.
_917416
710 2 _aTaylor and Francis.
_910719
776 0 8 _iPrint version:
_z9781498783590
_w(DLC) 2016051118
856 4 0 _uhttps://www.taylorfrancis.com/books/9781315191089
_zClick here to view.
942 _cEBK
999 _c71521
_d71521