| 000 | 03925nam a22005295i 4500 | ||
|---|---|---|---|
| 001 | 978-3-030-20721-2 | ||
| 003 | DE-He213 | ||
| 005 | 20220801215733.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 190530s2019 sz | s |||| 0|eng d | ||
| 020 |
_a9783030207212 _9978-3-030-20721-2 |
||
| 024 | 7 |
_a10.1007/978-3-030-20721-2 _2doi |
|
| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aSkliarova, Iouliia. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _946162 |
|
| 245 | 1 | 0 |
_aFPGA-BASED Hardware Accelerators _h[electronic resource] / _cby Iouliia Skliarova, Valery Sklyarov. |
| 250 | _a1st ed. 2019. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2019. |
|
| 300 |
_aXVI, 245 p. _bonline resource. |
||
| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
||
| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
||
| 490 | 1 |
_aLecture Notes in Electrical Engineering, _x1876-1119 ; _v566 |
|
| 505 | 0 | _aReconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design. | |
| 520 | _aThis book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
|
| 650 | 0 |
_aComputational intelligence. _97716 |
|
| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _946163 |
| 650 | 2 | 4 |
_aComputational Intelligence. _97716 |
| 700 | 1 |
_aSklyarov, Valery. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _946164 |
|
| 710 | 2 |
_aSpringerLink (Online service) _946165 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030207205 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030207229 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030207236 |
| 830 | 0 |
_aLecture Notes in Electrical Engineering, _x1876-1119 ; _v566 _946166 |
|
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-030-20721-2 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cEBK | ||
| 999 |
_c77811 _d77811 |
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