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001 978-3-030-51610-9
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020 _a9783030516109
_9978-3-030-51610-9
024 7 _a10.1007/978-3-030-51610-9
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aGhavami, Behnam.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_947299
245 1 0 _aSoft Error Reliability of VLSI Circuits
_h[electronic resource] :
_bAnalysis and Mitigation Techniques /
_cby Behnam Ghavami, Mohsen Raji.
250 _a1st ed. 2021.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2021.
300 _aXIII, 114 p. 39 illus., 9 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction: Soft Error Modeling -- Soft Error Rate Estimation of VLSI circuits -- Process Variation Aware Soft Error Rate Estimation Method for Integrated Circuits -- GPU-Accelerated Soft Error Rate Analysis of Large-scale Integrated Circuits -- FPGA Hardware Acceleration of Soft Error Rate Estimation of Digital Circuits -- Soft Error Tolerant Circuit Design using Partitioning-based Gate Sizing -- Resynthesize Technique for Soft Error Tolerant Design of Combinational Circuits.
520 _aThis book is intended for readers who are interested in the design of robust and reliable electronic digital systems. The authors cover emerging trends in design of today’s reliable electronic systems which are applicable to safety-critical applications, such as automotive or healthcare electronic systems. The emphasis is on modeling approaches and algorithms for analysis and mitigation of soft errors in nano-scale CMOS digital circuits, using techniques that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. The authors introduce software tools for analysis and mitigation of soft errors in electronic systems, which can be integrated easily with design flows. In addition to discussing soft error aware analysis techniques for combinational logic, the authors also describe new soft error mitigation strategies targeting commercial digital circuits. Coverage includes novel Soft Error Rate (SER) analysis techniques such as process variation aware SER estimation and GPU accelerated SER analysis techniques, in addition to SER reduction methods such as gate sizing and logic restructuring based SER techniques. Provides an accessible, comprehensive introduction to soft errors; Describes an easy to follow procedure for modeling, analysis, and estimation of soft error rate of digital circuits; Includes state-of-the art soft error aware CAD algorithms; Describes practical soft error aware synthesis techniques for commercial large-scale VLSI designs.
650 0 _aElectronic circuits.
_919581
650 0 _aElectronics.
_93425
650 0 _aCooperating objects (Computer systems).
_96195
650 1 4 _aElectronic Circuits and Systems.
_947300
650 2 4 _aElectronics and Microelectronics, Instrumentation.
_932249
650 2 4 _aCyber-Physical Systems.
_932475
700 1 _aRaji, Mohsen.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_947301
710 2 _aSpringerLink (Online service)
_947302
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783030516093
776 0 8 _iPrinted edition:
_z9783030516116
776 0 8 _iPrinted edition:
_z9783030516123
856 4 0 _uhttps://doi.org/10.1007/978-3-030-51610-9
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c78012
_d78012