000 03313nam a22005175i 4500
001 978-981-33-4642-0
003 DE-He213
005 20220801220118.0
007 cr nn 008mamaa
008 210106s2021 si | s |||| 0|eng d
020 _a9789813346420
_9978-981-33-4642-0
024 7 _a10.1007/978-981-33-4642-0
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aTaraate, Vaibbhav.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_948411
245 1 0 _aASIC Design and Synthesis
_h[electronic resource] :
_bRTL Design Using Verilog /
_cby Vaibbhav Taraate.
250 _a1st ed. 2021.
264 1 _aSingapore :
_bSpringer Nature Singapore :
_bImprint: Springer,
_c2021.
300 _aXXI, 330 p. 311 illus., 184 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aChapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
520 _aThis book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprogramming .
_932081
650 0 _aLogic design.
_93686
650 1 4 _aElectronic Circuits and Systems.
_948412
650 2 4 _aControl Structures and Microprogramming.
_932083
650 2 4 _aLogic Design.
_93686
710 2 _aSpringerLink (Online service)
_948413
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9789813346413
776 0 8 _iPrinted edition:
_z9789813346437
776 0 8 _iPrinted edition:
_z9789813346444
856 4 0 _uhttps://doi.org/10.1007/978-981-33-4642-0
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c78214
_d78214