000 | 03498nam a22005175i 4500 | ||
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001 | 978-3-319-23389-5 | ||
003 | DE-He213 | ||
005 | 20220801220923.0 | ||
007 | cr nn 008mamaa | ||
008 | 151114s2016 sz | s |||| 0|eng d | ||
020 |
_a9783319233895 _9978-3-319-23389-5 |
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024 | 7 |
_a10.1007/978-3-319-23389-5 _2doi |
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050 | 4 | _aTK7867-7867.5 | |
072 | 7 |
_aTJFC _2bicssc |
|
072 | 7 |
_aTEC008010 _2bisacsh |
|
072 | 7 |
_aTJFC _2thema |
|
082 | 0 | 4 |
_a621.3815 _223 |
245 | 1 | 0 |
_aNear Threshold Computing _h[electronic resource] : _bTechnology, Methods and Applications / _cedited by Michael Hübner, Cristina Silvano. |
250 | _a1st ed. 2016. | ||
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2016. |
|
300 |
_aIX, 101 p. 56 illus., 37 illus. in color. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
||
338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _aPART I: NTC opportunities, challenges and limits -- Chapter 1: Extreme Energy Efficiency by Near Threshold Voltage Operation -- Part II Micro-architecture challenges and energy management at NTC -- Chapter2: Many-core Architecture for NTC: Energy Efficiency from the Ground Up -- Chapter 3: Variability-Aware Voltage Island Management for Near-Threshold Voltage Computing With Performance Guarantees -- Part III Memory system design for NTC -- Chapter4: Resizable Data Composer (RDC) Cache: A Near-Threshold Cache tolerating Process Variation Via architectural fault tolerance -- Chapter 5 Memories for NTC. | |
520 | _aThis book explores near-threshold computing (NTC), a design-space using techniques to run digital chips (processors) near the lowest possible voltage. Readers will be enabled with specific techniques to design chips that are extremely robust; tolerating variability and resilient against errors. Variability-aware voltage and frequency allocation schemes will be presented that will provide performance guarantees, when moving toward near-threshold manycore chips. · Provides an introduction to near-threshold computing, enabling reader with a variety of tools to face the challenges of the power/utilization wall; · Demonstrates how to design efficient voltage regulation, so that each region of the chip can operate at the most efficient voltage and frequency point; · Investigates how performance guarantees can be ensured when moving towards NTC manycores through variability-aware voltage and frequency allocation schemes. . | ||
650 | 0 |
_aElectronic circuits. _919581 |
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650 | 0 |
_aMicroprocessors. _953121 |
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650 | 0 |
_aComputer architecture. _93513 |
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650 | 1 | 4 |
_aElectronic Circuits and Systems. _953122 |
650 | 2 | 4 |
_aProcessor Architectures. _953123 |
700 | 1 |
_aHübner, Michael. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt _953124 |
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700 | 1 |
_aSilvano, Cristina. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt _953125 |
|
710 | 2 |
_aSpringerLink (Online service) _953126 |
|
773 | 0 | _tSpringer Nature eBook | |
776 | 0 | 8 |
_iPrinted edition: _z9783319233888 |
776 | 0 | 8 |
_iPrinted edition: _z9783319233901 |
776 | 0 | 8 |
_iPrinted edition: _z9783319372099 |
856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-319-23389-5 |
912 | _aZDB-2-ENG | ||
912 | _aZDB-2-SXE | ||
942 | _cEBK | ||
999 |
_c79089 _d79089 |