000 03398nam a22005055i 4500
001 978-3-319-27177-4
003 DE-He213
005 20220801221028.0
007 cr nn 008mamaa
008 160223s2016 sz | s |||| 0|eng d
020 _a9783319271774
_9978-3-319-27177-4
024 7 _a10.1007/978-3-319-27177-4
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aBindal, Ahmet.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_953739
245 1 0 _aSilicon Nanowire Transistors
_h[electronic resource] /
_cby Ahmet Bindal, Sotoudeh Hamedi-Hagh.
250 _a1st ed. 2016.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2016.
300 _aXIV, 165 p. 145 illus., 5 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aDual Work Function Silicon Nanowire MOS Transistors -- Single Work Function Silicon Nanowire MOS Transistors -- Spice Modeling For Analog and Digital Applications -- High-Speed Analog Applications -- Radio Frequency (RF) Applications -- SRAM Mega Cell Design for Digital Applications -- Field-Programmable-Gate-Array (FPGA) -- Integrate-And-Fire Spiking (IFS) Neuron -- Direct Sequence Spread Spectrum (DSSS) Base-Band Transmitter.-.
520 _aThis book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types of memory on the same chip, such as capacitive cells and transistors with floating gates that can be used as DRAMs and Flash memories.
650 0 _aElectronic circuits.
_919581
650 0 _aNanotechnology.
_94707
650 1 4 _aElectronic Circuits and Systems.
_953740
650 2 4 _aNanotechnology.
_94707
700 1 _aHamedi-Hagh, Sotoudeh.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_953741
710 2 _aSpringerLink (Online service)
_953742
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783319271750
776 0 8 _iPrinted edition:
_z9783319271767
776 0 8 _iPrinted edition:
_z9783319800851
856 4 0 _uhttps://doi.org/10.1007/978-3-319-27177-4
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c79211
_d79211