| 000 | 03651nam a22005295i 4500 | ||
|---|---|---|---|
| 001 | 978-3-319-59418-7 | ||
| 003 | DE-He213 | ||
| 005 | 20220801222403.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 170628s2018 sz | s |||| 0|eng d | ||
| 020 |
_a9783319594187 _9978-3-319-59418-7 |
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| 024 | 7 |
_a10.1007/978-3-319-59418-7 _2doi |
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| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
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| 072 | 7 |
_aTEC008010 _2bisacsh |
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| 072 | 7 |
_aTJFC _2thema |
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| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aMehta, Ashok B. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _961220 |
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| 245 | 1 | 0 |
_aASIC/SoC Functional Design Verification _h[electronic resource] : _bA Comprehensive Guide to Technologies and Methodologies / _cby Ashok B. Mehta. |
| 250 | _a1st ed. 2018. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2018. |
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| 300 |
_aXXXI, 328 p. 175 illus., 160 illus. in color. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 505 | 0 | _aChapter 1.Introduction -- Chapter 2.Functional Verification- Challeenges and Solution -- Chapter 3.SystemVerilog Paradigm -- Chapter 4. UVM -- Chapter 5.CRV -- Chapter 6.SVA -- Chapter 7.SFC -- Chapter 8.CDC -- Chapter 9.Low Power Verification -- Chapter 10. Static Verification -- Chapter 11.ESL -- Chapter 12. Hardware/Software Co-verification -- Chapter 13 -- Analog Mixed Signals Verification -- Chapter 14 -- SOC Interconnect Verification -- Chapter 15. The Complete Product Design Lifecycle -- Chapter 16. Voice Over IP -- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based -- Chapter 18. Cache Memory Subsystem Verification: ISS Based. | |
| 520 | _aThis book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
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| 650 | 0 |
_aMicroprocessors. _961221 |
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| 650 | 0 |
_aComputer architecture. _93513 |
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| 650 | 0 |
_aLogic design. _93686 |
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| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _961222 |
| 650 | 2 | 4 |
_aProcessor Architectures. _961223 |
| 650 | 2 | 4 |
_aLogic Design. _93686 |
| 710 | 2 |
_aSpringerLink (Online service) _961224 |
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| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319594170 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319594194 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319866208 |
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-319-59418-7 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cEBK | ||
| 999 |
_c80713 _d80713 |
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