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001 978-3-319-54313-0
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020 _a9783319543130
_9978-3-319-54313-0
024 7 _a10.1007/978-3-319-54313-0
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
245 1 0 _aNeuro-inspired Computing Using Resistive Synaptic Devices
_h[electronic resource] /
_cedited by Shimeng Yu.
250 _a1st ed. 2017.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2017.
300 _aXI, 269 p. 190 illus., 79 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aChapter1: Introduction to Neuro-Inspired Computing using Resistive Synaptic Devices -- Part I: Device-level Demonstrations of Resistive Synaptic Devices -- Chapter2: Phase Change Memory based Synaptic Devices -- Chapter3: Pr0.7Ca0.3MnO3 (PCMO) based Synaptic Devices -- Chapter4: TaOx/TiO2 based Synaptic Devices -- Part II: Array-level Demonstrations of Resistive Synaptic Devices and Neural Networks -- Chapter5: Training and Inference in Hopfield Network using 10×10 Phase Change Synaptic Array -- Chapter6: Experimental Demonstration of Firing-Rate Neural Networks based on Metal-Oxide Memristive Crossbars -- Chapter7: Weight Tuning of Resistive Synaptic Devices and Convolution Kernel Operation on 12×12 Cross-Point Array -- Chapter8: Spiking Neural Network with 256×256 PCM Array -- Part III: Circuit, Architecture and Algorithm-level Design of Resistive Synaptic Devices based Neuromorphic System -- Chapter9: Peripheral Circuit Design Considerations of Neuro-inspired Architectures -- Chapter10: Processing-in-Memory Architecture Design for Accelerating Neuro-Inspired Algorithms -- Chapter11: Multi-layer Perceptron Algorithm: Impact of Non-Ideal Conductance and Area-Efficient Peripheral Circuits -- Chapter12: Impact of Non-Ideal Resistive Synaptic Device Behaviors on Implementation of Sparse Coding Algorithm -- Chapter13: Binary OxRAM/CBRAM Memories for Efficient Implementations of Embedded Neuromorphic Circuits.
520 _aThis book summarizes the recent breakthroughs in hardware implementation of neuro-inspired computing using resistive synaptic devices. The authors describe how two-terminal solid-state resistive memories can emulate synaptic weights in a neural network. Readers will benefit from state-of-the-art summaries of resistive synaptic devices, from the individual cell characteristics to the large-scale array integration. This book also discusses peripheral neuron circuits design challenges and design strategies. Finally, the authors describe the impact of device non-ideal properties (e.g. noise, variation, yield) and their impact on the learning performance at the system-level, using a device-algorithm co-design methodology. • Provides single-source reference to recent breakthroughs in resistive synaptic devices, not only at individual cell-level, but also at integrated array-level; • Includes detailed discussion of the peripheral circuits and array architecture design of the neuro-crossbar system; • Focuses on new experimental results that are likely to solve practical, artificial intelligent problems, such as image classification.
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprocessors.
_962449
650 0 _aComputer architecture.
_93513
650 1 4 _aElectronic Circuits and Systems.
_962450
650 2 4 _aProcessor Architectures.
_962451
700 1 _aYu, Shimeng.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_962452
710 2 _aSpringerLink (Online service)
_962453
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783319543123
776 0 8 _iPrinted edition:
_z9783319543147
776 0 8 _iPrinted edition:
_z9783319853680
856 4 0 _uhttps://doi.org/10.1007/978-3-319-54313-0
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c80975
_d80975