000 | 03665nam a22005415i 4500 | ||
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001 | 978-3-319-54714-5 | ||
003 | DE-He213 | ||
005 | 20220801222653.0 | ||
007 | cr nn 008mamaa | ||
008 | 170320s2017 sz | s |||| 0|eng d | ||
020 |
_a9783319547145 _9978-3-319-54714-5 |
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024 | 7 |
_a10.1007/978-3-319-54714-5 _2doi |
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_a621.3815 _223 |
100 | 1 |
_aWang, Ran. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _962719 |
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245 | 1 | 0 |
_aTesting of Interposer-Based 2.5D Integrated Circuits _h[electronic resource] / _cby Ran Wang, Krishnendu Chakrabarty. |
250 | _a1st ed. 2017. | ||
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2017. |
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300 |
_aXIV, 182 p. 118 illus., 102 illus. in color. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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_atext file _bPDF _2rda |
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505 | 0 | _aIntroduction -- Pre-Bond Testing of the Silicon Interposer -- Post-Bond Scan-based Testing of Interposer Interconnects -- Test Architecture and Test-Path Scheduling -- Built-In Self-Test -- ExTest Scheduling and Optimization -- A Programmable Method for Low-Power Scan Shift in SoC Dies -- Conclusions.-. | |
520 | _aThis book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. | ||
650 | 0 |
_aElectronic circuits. _919581 |
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650 | 0 |
_aMicroprocessors. _962720 |
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650 | 0 |
_aComputer architecture. _93513 |
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650 | 0 |
_aLogic design. _93686 |
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650 | 1 | 4 |
_aElectronic Circuits and Systems. _962721 |
650 | 2 | 4 |
_aProcessor Architectures. _962722 |
650 | 2 | 4 |
_aLogic Design. _93686 |
700 | 1 |
_aChakrabarty, Krishnendu. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _914047 |
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710 | 2 |
_aSpringerLink (Online service) _962723 |
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773 | 0 | _tSpringer Nature eBook | |
776 | 0 | 8 |
_iPrinted edition: _z9783319547138 |
776 | 0 | 8 |
_iPrinted edition: _z9783319547152 |
776 | 0 | 8 |
_iPrinted edition: _z9783319854618 |
856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-319-54714-5 |
912 | _aZDB-2-ENG | ||
912 | _aZDB-2-SXE | ||
942 | _cEBK | ||
999 |
_c81027 _d81027 |