000 04156nam a22005655i 4500
001 978-3-031-79815-3
003 DE-He213
005 20240730164157.0
007 cr nn 008mamaa
008 220601s2010 sz | s |||| 0|eng d
020 _a9783031798153
_9978-3-031-79815-3
024 7 _a10.1007/978-3-031-79815-3
_2doi
050 4 _aT1-995
072 7 _aTBC
_2bicssc
072 7 _aTEC000000
_2bisacsh
072 7 _aTBC
_2thema
082 0 4 _a620
_223
100 1 _aLi, Lun.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_982591
245 1 0 _aDigital System Verification
_h[electronic resource] :
_bA Combined Formal Methods and Simulation Framework /
_cby Lun Li, Mitchel Thornton.
250 _a1st ed. 2010.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2010.
300 _aXIV, 79 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSynthesis Lectures on Digital Circuits & Systems,
_x1932-3174
505 0 _aIntroduction -- Formal Methods Background -- Simulation Approaches -- Integrated Design Validation System -- Conclusion and Summary.
520 _aIntegrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques. Formal techniques have been emerging as commercialized EDA tools in the past decade. Simulation remains a predominantly used tool to validate a design in industry. After more than 50 years of development, simulation methods have reached a degree of maturity, however, new advances continue to be developed in the area. A simulation approach for functional verification can theoretically validate all possible behaviors of a design but requires excessive computational resources. Rapidly evolving markets demand short design cycles while the increasing complexity of a design causes simulation approaches to provide less and less coverage. Formal verification is an attractive alternative since 100% coverage can be achieved; however, large designs impose unrealistic computational requirements. Combining formal verification and simulation into a single integrated circuit validation framework is an attractive alternative. This book focuses on an Integrated Design Validation (IDV) system that provides a framework for design validation and takes advantage of current technology in the areas of simulation and formal verification resulting in a practical validation engine with reasonable runtime. After surveying the basic principles of formal verification and simulation, this book describes the IDV approach to integrated circuit functional validation. Table of Contents: Introduction / Formal Methods Background / Simulation Approaches / Integrated Design Validation System/ Conclusion and Summary.
650 0 _aEngineering.
_99405
650 0 _aElectronic circuits.
_919581
650 0 _aControl engineering.
_931970
650 0 _aRobotics.
_92393
650 0 _aAutomation.
_92392
650 0 _aComputers.
_98172
650 1 4 _aTechnology and Engineering.
_982595
650 2 4 _aElectronic Circuits and Systems.
_982597
650 2 4 _aControl, Robotics, Automation.
_931971
650 2 4 _aComputer Hardware.
_933420
700 1 _aThornton, Mitchel.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_982598
710 2 _aSpringerLink (Online service)
_982601
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783031798146
776 0 8 _iPrinted edition:
_z9783031798160
830 0 _aSynthesis Lectures on Digital Circuits & Systems,
_x1932-3174
_982603
856 4 0 _uhttps://doi.org/10.1007/978-3-031-79815-3
912 _aZDB-2-SXSC
942 _cEBK
999 _c85378
_d85378