Logic Synthesis and SOC Prototyping (Record no. 76051)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 02788nam a22005175i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-981-15-1314-5 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220801214201.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 200102s2020 si | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9789811513145 |
| -- | 978-981-15-1314-5 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Taraate, Vaibbhav. |
| 245 10 - TITLE STATEMENT | |
| Title | Logic Synthesis and SOC Prototyping |
| Sub Title | RTL Design using VHDL / |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2020. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XIX, 251 p. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Introduction -- ASIC Design and SOC prototype -- Design using VHDL & Guidelines -- Design using VHDL & Guidelines -- Design and Verification Strategies -- VHDL Design and RTL Tweaks -- ASIC Synthesis and Design Constraints -- Design optimization -- Design optimization -- FPGA for SOC Prototype -- Prototype using Single and Multiple FPGA. . |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-981-15-1314-5 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Singapore : |
| -- | Springer Nature Singapore : |
| -- | Imprint: Springer, |
| -- | 2020. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprogramming . |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic design. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Control Structures and Microprogramming. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic Design. |
| 912 ## - | |
| -- | ZDB-2-ENG |
| 912 ## - | |
| -- | ZDB-2-SXE |
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