Formal Verification of Simulink/Stateflow Diagrams (Record no. 80865)
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000 -LEADER | |
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fixed length control field | 03444nam a22005295i 4500 |
001 - CONTROL NUMBER | |
control field | 978-3-319-47016-0 |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20220801222527.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 161107s2017 sz | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 9783319470160 |
-- | 978-3-319-47016-0 |
082 04 - CLASSIFICATION NUMBER | |
Call Number | 621.3815 |
100 1# - AUTHOR NAME | |
Author | Zhan, Naijun. |
245 10 - TITLE STATEMENT | |
Title | Formal Verification of Simulink/Stateflow Diagrams |
Sub Title | A Deductive Approach / |
250 ## - EDITION STATEMENT | |
Edition statement | 1st ed. 2017. |
300 ## - PHYSICAL DESCRIPTION | |
Number of Pages | XV, 258 p. 74 illus., 60 illus. in color. |
505 0# - FORMATTED CONTENTS NOTE | |
Remark 2 | 1 Introduction -- 2 Preliminaries -- 3 Unifying Theories of Programming -- 4 Simulink -- 5 Stateflow and Its Combination with Simulink -- 6 Hybrid CSP -- 7 Hybrid Hoare Logic -- 8 The HHL Prover -- 9 Invariant Generation -- 10 Translating Simulink Diagrams into HCSP -- 11 Translating Simulink/Stateflow Diagrams into HCSP -- 12 From HCSP to Simulink -- 13 MARS A Toolkit for Modelling, Analysis and Verification of Hybrid Systems -- 14 Case Studies. |
520 ## - SUMMARY, ETC. | |
Summary, etc | This book presents a state-of-the-art technique for formal verification of continuous-time Simulink/Stateflow diagrams, featuring an expressive hybrid system modelling language, a powerful specification logic and deduction-based verification approach, and some impressive, realistic case studies. Readers will learn the HCSP/HHL-based deductive method and the use of corresponding tools for formal verification of Simulink/Stateflow diagrams. They will also gain some basic ideas about fundamental elements of formal methods such as formal syntax and semantics, and especially the common techniques applied in formal modelling and verification of hybrid systems. By investigating the successful case studies, readers will realize how to apply the pure theory and techniques to real applications, and hopefully will be inspired to start to use the proposed approach, or even develop their own formal methods in their future work. |
700 1# - AUTHOR 2 | |
Author 2 | Wang, Shuling. |
700 1# - AUTHOR 2 | |
Author 2 | Zhao, Hengjun. |
856 40 - ELECTRONIC LOCATION AND ACCESS | |
Uniform Resource Identifier | https://doi.org/10.1007/978-3-319-47016-0 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | eBooks |
100 1# - AUTHOR NAME | |
-- | (orcid)0000-0003-3298-3817 |
-- | https://orcid.org/0000-0003-3298-3817 |
264 #1 - | |
-- | Cham : |
-- | Springer International Publishing : |
-- | Imprint: Springer, |
-- | 2017. |
336 ## - | |
-- | text |
-- | txt |
-- | rdacontent |
337 ## - | |
-- | computer |
-- | c |
-- | rdamedia |
338 ## - | |
-- | online resource |
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347 ## - | |
-- | text file |
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-- | rda |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronic circuits. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Microprocessors. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Computer architecture. |
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronic Circuits and Systems. |
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Processor Architectures. |
912 ## - | |
-- | ZDB-2-ENG |
912 ## - | |
-- | ZDB-2-SXE |
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