Digital Design
By: Mano, M. Morris
| Ciletti, Michael. D.
Material type: 
BookPublisher: New Delhi Pearson 2008Edition: 4.Description: p.622.ISBN: 9788131714508.Subject(s): Asynchronous Sequential Logic | Gate Level Minimization | Registers and CountersDDC classification: 621.381958 M280
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CENTRAL LIBRARY | 621.381958 M280 (Browse shelf) | Checked out | 11/26/2024 | G02892 |
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