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Using Artificial Neural Networks for Analog Integrated Circuit Design Automation [electronic resource] / by João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins, Nuno C. C. Lourenço.

By: Rosa, João P. S [author.].
Contributor(s): Guerra, Daniel J. D [author.] | Horta, Nuno C. G [author.] | Martins, Ricardo M. F [author.] | Lourenço, Nuno C. C [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: SpringerBriefs in Applied Sciences and Technology: Publisher: Cham : Springer International Publishing : Imprint: Springer, 2020Edition: 1st ed. 2020.Description: XVIII, 101 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783030357436.Subject(s): Electronic circuits | Signal processing | Computational intelligence | Electronic Circuits and Systems | Signal, Speech and Image Processing | Computational IntelligenceAdditional physical formats: Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Introduction -- Related Work -- Overview of Artificial Neural Networks (ANNs) -- On the Exploration of Promising Analog IC Designs via ANNs -- ANNs as an Alternative for Automatic Analog IC Placement -- Conclusions. .
In: Springer Nature eBookSummary: This book addresses the automatic sizing and layout of analog integrated circuits (ICs) using deep learning (DL) and artificial neural networks (ANN). It explores an innovative approach to automatic circuit sizing where ANNs learn patterns from previously optimized design solutions. In opposition to classical optimization-based sizing strategies, where computational intelligence techniques are used to iterate over the map from devices’ sizes to circuits’ performances provided by design equations or circuit simulations, ANNs are shown to be capable of solving analog IC sizing as a direct map from specifications to the devices’ sizes. Two separate ANN architectures are proposed: a Regression-only model and a Classification and Regression model. The goal of the Regression-only model is to learn design patterns from the studied circuits, using circuit’s performances as input features and devices’ sizes as target outputs. This model can size a circuit given its specifications for a single topology. The Classification and Regression model has the same capabilities of the previous model, but it can also select the most appropriate circuit topology and its respective sizing given the target specification. The proposed methodology was implemented and tested on two analog circuit topologies. .
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Introduction -- Related Work -- Overview of Artificial Neural Networks (ANNs) -- On the Exploration of Promising Analog IC Designs via ANNs -- ANNs as an Alternative for Automatic Analog IC Placement -- Conclusions. .

This book addresses the automatic sizing and layout of analog integrated circuits (ICs) using deep learning (DL) and artificial neural networks (ANN). It explores an innovative approach to automatic circuit sizing where ANNs learn patterns from previously optimized design solutions. In opposition to classical optimization-based sizing strategies, where computational intelligence techniques are used to iterate over the map from devices’ sizes to circuits’ performances provided by design equations or circuit simulations, ANNs are shown to be capable of solving analog IC sizing as a direct map from specifications to the devices’ sizes. Two separate ANN architectures are proposed: a Regression-only model and a Classification and Regression model. The goal of the Regression-only model is to learn design patterns from the studied circuits, using circuit’s performances as input features and devices’ sizes as target outputs. This model can size a circuit given its specifications for a single topology. The Classification and Regression model has the same capabilities of the previous model, but it can also select the most appropriate circuit topology and its respective sizing given the target specification. The proposed methodology was implemented and tested on two analog circuit topologies. .

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